1. Field of the Invention
The present invention relates to a multilayer printed wiring board for mounting a semiconductor element and, more particularly, to a multilayer printed wiring board that improves the connection reliability of a semiconductor element.
2. Description of Background Art
Semiconductor elements may be mounted on multilayer printed wiring boards of a so-called package-on-package (PoP) type. Namely, on the horizontally central part of the front surface of a multilayer printed wiring board set as a package substrate, a first semiconductor element (for example, a CPU chip) is directly mounted; and on the front surface of the first multilayer printed wiring board, a second printed wiring board set as a package substrate with a mounted second semiconductor element (for example, a memory chip) is formed to have a greater size than the first semiconductor element and covers the first semiconductor element.
On such a PoP-type printed wiring board, a conductive circuit on the front surface of the printed wiring board is connected to the first semiconductor element through first solder bumps formed on solder pads positioned in the central part on the front surface, while connecting the conductive circuit to the second printed wiring board through second solder bumps, which are set taller than the first solder bumps and are positioned on the solder pads to surround the solder pads in the central part. Moreover, a conductive circuit on the back surface, the other surface of the multilayer printed wiring board, is connected to a motherboard or the like using solder balls (BGA) on solder pads formed in a grid on the back surface (for an example, refer to JP 2008-177503 A). These connections are achieved by using heat to reflow the solder bumps, whose end portions are substantially hemispherical. The entire contents of this publication are incorporated herein by reference.